? semiconductor components industries, llc, 2005 august, 2005 ? rev. 1 1 publication order number: BSR58LT1/d BSR58LT1 jfet chopper transistor n?channel ? depletion features ? pb?free package is available maximum ratings rating symbol value unit drain ?gate voltage v dg ?40 vdc gate ?source voltage v gs ?35 vdc gate current i g 50 madc total device dissipation @ t a = 25 c derate above 25 c p d 350 2.8 mw mw/ c lead temperature t l 300 c operating and storage junction temperature range t j , t stg ?65 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics gate ?source breakdown voltage (i g = ?1.0 adc) v (br)gss 40 ? vdc gate reverse current (v gs = ?15 vdc) i gss ? ? 1.0 nadc gate source cutoff voltage (v ds = 5.0 vdc, i d = 1.0 adc) v gs(off) ?0.8 ?4.0 vdc drain?cutoff current (v ds = 5.0 vdc, v gs = ?10 vdc) i d(off) ? 1.0 nadc on characteristics zero?gate?voltage drain current (note 1) (v ds = 15 vdc) i dss 8.0 80 madc static drain?source on resistance (v ds = 0.1 vdc) r ds(on) ? 60 drain gate and source gate on?capacitance (v ds = v gs = 0, f = 1.0 mhz) c dg(on) + c sg(on) ? 28 pf drain gate off?capacitance (v gs = ?10 vdc, f = 1.0 mhz) c dg(off) ? 5.0 pf source gate off?capacitance (v gs = ?10 vdc, f = 1.0 mhz) c sg(off) ? 5.0 pf 1. pulse width = 300 s, duty cycle = 3.0%. device package shipping ? ordering information BSR58LT1 sot?23 sot?23 case 318 style 10 3000/tape & reel 3 2 1 marking diagram m6m http://onsemi.com 1 drain 2 source 3 gate BSR58LT1g sot?23 (pb?free) 3000/tape & reel m6 = device code m = date code* = pb?free package (note: microdot may be in either location) *date code orientation and/or overbar may vary depending upon manufacturing location. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d.
BSR58LT1 http://onsemi.com 2 t f , fall time (ns) t r , rise time (ns) t d(on) , turn?on delay time (ns) 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 1. turn?on delay time r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v r k = r d 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 2. rise time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 3. turn?off delay time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v t d(off) , turn?off delay time (ns) 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 4. fall time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v typical switching characteristics note 1 the switching characteristics shown above were measured using a test circuit similar to figure 5. at the beginning of the switching interval, the gate voltage is at gate supply v oltage (?v gg ). the drain?source voltage (v ds ) is slightly lower than drain supply voltage (v dd ) due to the voltage divider. thus reverse transfer capacitance (c rss ) or gate?drain capacitance (c gd ) is charged to v gg + v ds . during the turn?on interval, gate?source capacitance (c gs ) discharges through the series combination of r gen and r k . c gd must discharge to v ds(on) through r g and r k in series with the parallel combination of effective load impedance (r d ) and drain?source resistance (r ds ). during the turn?off, this charge flow is reversed. predicting turn?on time is somewhat difficult as the channel resistance r ds is a function of the gate?source voltage. while c gs discharges, v gs approaches zero and r ds decreases. since c gd discharges through r ds , turn?on time is non?linear. during turn?off, the situation is reversed with r ds increasing as c gd charges. the above switching curves show two impedance conditions; 1) r k is equal to r d , which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) r k = 0 (low impedance) the driving source impedance is that of the generator. r gen 50 v gen input r k 50 r gg v gg 50 output r d +v dd r t set v ds(off) = 10 v input pulse t r t f pulse width duty cycle 0.25 ns 0.5 ns = 2.0 s 2.0% r gg r k r d r d (r t 50) r d r t 50 figure 5. switching time test circuit
BSR58LT1 http://onsemi.com 3 r ds(on) , drain?source on?state resistance (ohms) note 2 the zero?gate?v oltage drain current (i dss ), is the principle determinant of other j-fet char acteristics. figure 10 shows the relationship of gate?source off voltage (v gs(off) and drain? source on resistance (r ds(on) ) to i dss . most of the devices will be within 10% of the values shown in figure 10. this data wil l be useful in predicting the char acteristic variations for a given part number. for example: unknown r ds(on) and v gs range for an j112 the electrical characteristics tabl e indicates that an j112 has an i dss range of 25 to 75 ma. figure 10, shows r ds(on) = 52 for i dss = 25 ma and 30 for i dss = 75 ma. the corresponding v gs values are 2.2 v and 4.8 v. y fs , forward transfer admittance (mmhos) c, capacitance (pf) r ds(on) , drain?source on?state resistance (ohms) r ds(on) , drain?source on?state resistance (normalized) 2.0 3.0 5.0 7.0 10 20 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 6. typical forward transfer admittance 1.0 1.5 2.0 3.0 5.0 7.0 10 15 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30 v r , reverse voltage (volts) figure 7. typical capacitance 200 160 120 80 40 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 v gs , gate?source voltage (volts) figure 8. effect of gate?source voltage on drain?source resistance 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 ?70 ?40 ?10 20 50 80 110 140 170 t channel , channel temperature ( c) figure 9. effect of temperature on drain?source on?state resistance j113 j112 j111 t channel = 25 c v ds = 15 v c gs c gd t channel = 25 c (c ds is negligible) i dss = 10 ma 25 ma 50ma 75ma 100ma 125ma t channel = 25 c i d = 1.0 ma v gs = 0 10 i dss , zero?gate?voltage drain current (ma) figure 10. effect of i dss on drain?source resistance and gate?source voltage 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 100 90 80 70 60 50 40 30 20 10 0 v gs , gate?source voltage (volts) t channel = 25 c r ds(on) @ v gs = 0 v gs(off)
BSR58LT1 http://onsemi.com 4 package dimensions b c l d a e a1 e 3 1 2 dim a min nom max min millimeters 0.89 1.00 1.11 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.37 0.44 0.50 0.015 c 0.09 0.13 0.18 0.003 d 2.80 2.90 3.04 0.110 e 1.20 1.30 1.40 0.047 e 1.78 1.90 2.04 0.070 l 0.35 0.54 0.69 0.014 2.10 2.40 2.64 0.083 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318?01 thru ?07 and ?09 obsolete, new standard 318?08. h e 0.040 0.044 0.002 0.004 0.018 0.020 0.005 0.007 0.114 0.120 0.051 0.055 0.075 0.081 0.021 0.029 0.094 0.104 nom max h e mm inches scale 10:1 0.8 0.031 0.9 0.035 0.95 0.037 0.95 0.037 2.0 0.079 sot?23 (to?236) case 318?08 issue al *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 10: pin 1. drain 2. source 3. gate on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 BSR58LT1/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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